[pci] PCI_T Not Asserting DEVSELn

[Dave Kroetsch <dkroetsch@videolocus.com>]

Another problem we're having is with the PCI_T path.   We're trying to 
DMA some long bursts in, and we seem to be dropping data.  The device 
is configured as a slow speed decode device.  We try to transfer 24 
words in (the FIFO depth for PCIW is 32).  This appears on the bus as
a 20 cycle burst (which works correctly), followed by a 2 cycle burst 
(which works correctly) and the next transaction begins, but the core 
never asserts DEVSELn.  It may be important to note that the 
transaction on the wishbone bus master begins JUST before this last 
transaction is to begin. 

Is there some reason that the PCI_T would not acknowledge the 
transaction in this case?

   Thanks,
        Dave Kroetsch
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