Re: [pci] Configuration Space Hanging

[Tadej Markovic <tadej@opencores.org>]

Hi Dave!


I read both your mails and I would need some more data. 

First I would like to how have you set user defined constants 
in the pci_user_constants.v file and if you have chaged any 
non-changable constants in the pci_constants.v file.

Second I would like to know, how did you set the registers in the configuration
space (Wishbone ERR could appear, if you want to access throug the image, which
does not exist - is not set in the configuration space OR if you access
through the I/O image with wrong byte select combination, etc.).

Third I would like to know more about your system environment. Where do you
have DMA on the PCI side? You probably have another PCI device, my guess is
not our PCI bridge, since you mentioned slow decoding response - our PCI
bridge has medium decode response time.

There is also another possibility, that you don't have the lates version of PCI
bridge. Some files were updated on the 5th of March, and top.v has had missing
include (some compilers needs it), which was updated on the 21st of March.

BTW: We did simulate simultaneous PCI Target / Master transactions on various
combinations of PCI and WB clock rates. If this is really a bug in our core, it
would be good to add the testcase.


Best regards,
	Tadej



On Wed, 15 May 2002, you wrote:
> We're running into a problem with the PCI configuration 
> space "hanging".  We are attempting to do simultaneous Target and 
> Initiator transfers when this occurs.  The wishbone and pci buses are 
> running synchronously.
> 
> The setup has a DMA coming IN the PCI_T and out of the wishbone
> master to a memory, and a DMA (using the OpenCore DMA Engine) out 
> through the wishbone slave to the PCI_I.  
> 
> This setup works for a few transactions, but then the wb_slave returns 
> an ERR, and stops the dma "out" of through the PCI_I.  At this point the 
> PCI configuration space seems hung and returns all 0xffffffff.  However,
> wishbone transactions still work.  We still have access to devices on the 
> wishbone bus (hanging off wb_master), and can even continue to 
> operate outbound DMA transfers (wb_slave), but we cannot do this 
> simultaneously.
> 
> Has this type of functionality been tested?  Does anyone have any 
> thoughts on how to fix this?
> 
> Thanks,
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