I don't see a problem not clearing PICSR in SW.
The way I think most interrupt handling code running on various OR1200
systems is the following:
1) an interrupt happens, peripheral device will raise its int_o
2) PICSR will be set to 1 due to input interrupt raised
3) OR1200 will start interrupt exception, SR[IEE] will be cleared disabling
any further interrupt exceptions
4) Interrupt exception handler, clear interrupt in original device, this
will also result in clearing PICSR one clock later
This all goes back to the original point made months ago, which is that
this description of the PIC assumes that peripherals generate
level-triggered interrupts. That's fine, though it probably ought to
be explicitly documented in the architecture manual. (As was also