Re: [openrisc] Bugs detected on or1ksim

["Damjan Lampret" <lampret@opencores.org>]

I don't see a problem not clearing PICSR in SW.

The way I think most  interrupt handling code running on various OR1200
systems is the following:
1) an interrupt happens, peripheral device will raise its int_o
2) PICSR will be set to 1 due to input interrupt raised
3) OR1200 will start interrupt exception, SR[IEE] will be cleared disabling
any further interrupt exceptions
4) Interrupt exception handler, clear interrupt in original device, this
will also result in clearing PICSR one clock later
5) Enable interrupt exception by setting SR[IEE] to 1 (this step can be
performed also with l.rfe returning from exception handler back to
previously interrupted sw code)

As you can see there is no need for clearing PICSR.

One thing to point out - if you want to defer handling of device interrupt
for later (for example in real-time OS), what you should do is to mask
device causing current interrupt in PICMR and then reenaqble interrupt
exception.

The arch manual as it is right now is not saying whether you should clear
PICSR or not, I think this is more a matter of particular OS how device
drivers and interrupt exception handler is done. Of course what the arch
manual says and what is ineed important is that PICSR will automatically
clear its bit if oroginal device will lower interrupt request to PIC. So
this would imply that clearing PICSR is not needed.

regards,
Damjan

----- Original Message -----
From: "Robert Cragie" <rcc@jennic.com>
To: <openrisc@opencores.org>
Sent: Tuesday, June 10, 2003 1:26 AM
Subject: RE: [openrisc] Bugs detected on or1ksim


> It seems to me that the outcome is still unclear on this.
>
> As far as I can tell, the correct strategy is to clear the interrupt at
the
> *source* of the interrupt. You should NOT have to write a '1' to the
> corresponding bit in the PICSR as well UNLESS the interrupt specifically
> represents a latched transient condition. Even in this case, writing a '1'
> to the corresponding bit in the PICSR is simply a convenient way of
> effectively clearing the interrupt at source.
>
> Robert Cragie, Design Engineer
> _______________________________________________________________
> Jennic Ltd, Furnival Street, Sheffield, S1 4QT,  UK
> http://www.jennic.com  Tel: +44 (0) 114 281 2655
> _______________________________________________________________
>
> > -----Original Message-----
> > From: owner-openrisc@opencores.org
> > [mailto:owner-openrisc@opencores.org]On Behalf Of Scott Furman
> > Sent: 09 June 2003 20:02
> > To: openrisc@opencores.org
> > Subject: Re: [openrisc] Bugs detected on or1ksim
> >
> >
> > Damjan Lampret wrote:
> >
> > >And the manual was changed at that time. This is what correctly
> > the manual
> > >(in opencores cvs) says about PICSR:
> > >
> > >PICSR is used to determine the status of each interrupt input.
> > Bits in PICSR
> > >represent the status of the interrupt inputs and the actual
> > interrupt must
> > >be cleared in the
> > >device, which is the source of the interrupt.
> > >
> > >
> > I agree that the manual is correct.  I think the part that is missing is
> > that the interrupt must be cleared in both the device that generated the
> > interrupt *and* in the PIC.
> >
> > -Scott
> >
> >
> > --
> > To unsubscribe from openrisc mailing list please visit
> > http://www.opencores.org/mailinglists.shtml
> >
>
> --
> To unsubscribe from openrisc mailing list please visit
http://www.opencores.org/mailinglists.shtml
>

--
To unsubscribe from openrisc mailing list please visit http://www.opencores.org/mailinglists.shtml