[openrisc] or1200_defines.v bug?

[Jeff Hanoch <jeff@lowrance.com>]

Hi all,

I am trying to implement the or1200 into an FPGA development board (proprietary to my company) which uses an Altera FPGA.  I am commenting out the line in the or1200_defines.v which defines the OR1200_DU_TB_IMPLEMENTED because it uses the Xilinx rams.  Because this is not defined, I am getting a compile error on line 389 of the or1200_du.v file.  Here's the transcript:

vlog -work work +libext+.V+.v +incdir+src/toe +incdir+src/mem_ctrl +incdir+src/or1200 +incdir+src/models +incdir+src/dbg_interface /proj/oc/or1k/or1200/rtl/verilog/or1200_du.v
Model Technology ModelSim SE vlog 5.6b Compiler 2002.06 Jun 28 2002
-- Compiling module or1200_du
ERROR: /proj/oc/or1k/or1200/rtl/verilog/or1200_du.v(389): Undefined variable: tb_wadr

It looks like this tb_wadr variable is defined on line 248 within an 'ifdef OR1200_DU_TB_IMPLEMENTED, yet it is used on line 389 without the same 'ifdef.  It is inside an 'ifdef OR1200_DU_READREGS which is defined.

Maybe I am not allowed to have OR1200_DU_READREGS defined without having OR1200_DU_TB_IMPLEMENTED, but I don't see why I couldn't.

Could someone take a look at this for me?  I am probably the only person using Altera instead of Xilinx so this may not have ever been tried before.

Thanks,
Jeff