Re: [openrisc] Re: INT and CS on OR1K was: [oc] documentation problem

["Frédéric Renet" <f.renet@mipsys.com>]

> > IMHO ~CSn signals and ~IRQn should be out of the processor
> > core, they are independant.
> 
> And they are. This spec is about native bus and native BIU. Processor core
> has only one ~IRQ. And processor core doesn't have anything with ~CS. Chips
> selects are handled by BIU. Native BIU is not part of central processor
> core.
OOops! I just misunderstood it. Sorry about that.


> > Another solution used by ColdFire is to provide a special bus
> > acces where the core sample the interrupt vector  on the data bus
> > LSByte.
> >
> 
> I don't like this.

I see this solution as the easiest to design a custom interrupt 
controller. 
But i can leave without it.


What is the current solution?