[bluetooth] Re: Baseband core progress

[ChuanChew Sin <ccsin@k7mail.com>]

Hi Puloma,

I agree that the CRC Sample Data has been "Byte" swapped,I also got the same result as yours.

Hi Jamil,

I will do the design in Verilog Behaviral level,there might someone else doing the VHDL coding.It would be great that at the end of the project we have both Verilog and VHDL coding.


I had done CRC,FEC,HEC generator and the Scrambler with the testbench for each block. 

Now,I'm going to implement the Frequency Hopping selector block with Anil Nainwal,I hope that we can finish it in 2-3 weeks time.

For the BT simulator, I've tried Bluehoc(free) you can download it from http://www-124.ibm.com/developerworks/opensource/bluehoc/




Best regards.


Chuan Chew



----- Original Message ----- 
From: Puloma Mukherjee <puloma@e... > 
To: bluetooth@o...  
Date: Sun, 4 May 2003 13:09:26 -0400 (EDT) 
Subject: Re: [bluetooth] Baseband core progress 

> 
> 
> HI, 
> Yes I have completed the three blocks of HEC,CRS and FEC.BUt it is 
> all a 
> behavioral model.and about CRC I just have one doubt,I have asked 
> this 
> before,it appears that the result has to be byte swapped.IS this 
> correct 
> or have I made some mistake in the implementation. 
> I would like to be instructed on this ASAP so that I can send Jamil 
> the 
> code that I have made. 
> Also I am going to make the Access code generator today. 
> 
> On Sun, 4 May 2003, Jamil Khatib wrote: 
> 


 Jamil Khatib  <khatib@opencores.org> WROTE :- 

>From :  Jamil Khatib  <khatib@opencores.org>
TO :  bluetooth@opencores.org
CC :  ccsin@k7mail.com, puloma@ece.sunysb.edu, anilnainwal@sofblueindia.com
Subject : Baseband core progress

Hi all,

Here are my colcusions on who is goign to work on which blocks

ChuanChew Sin: ccsin@k7mail.com : 1 FEC 2 CRC 3 HEC 4 Hop frequency:
Behavioral Verilog

Puloma Mukherjee: puloma@ece.sunysb.edu: FEC HEC CRC  (Done)

Anil Nainwal - Sofblueindia: anilnainwal@sofblueindia.com: Frequency hopping,
Access code generation  Verilog and VHDL

It seems there are duplicates please let me know your decision.

Here are some other issues
- Once you provide me with your files I wil start integrating them and see
how they interact with each other, but please try to make the interfaces as
described in the spec and let me know if you have other comments on it.

- please try to make basic check for your blocks sing some test benches since
I am not going to test them.

- Let me know if I have to code other parts of the data path blocks.

- We have to try to have the blocks in both VHDL and Verilog so as to check
them together.

- I still do not know how can we check the whole system. Do you have any
suggestion? May be a BB SW simulator can be used to genertate the protocol
and the we test our design against it???

- The tools. I think I have to check this issue specially Altera but I think
I can get one or two maximum.

- I uploaded the latest design spec to
http://www.opencores.org/cores/bluetooth/Bluetooth.zip
please review it and let me know if it is OK so as to put it on the CVS

Regards,
Jamil KHatib

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