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Re: Re: Re: [bluetooth] FH Selector implementaion query...
Chuan,
The "mod" function seems only synthesis-able for arguments that are
power of 2. i.e ( y mod x ) x = 2^^(n) to achieve successful
synthesis.The fact behind this note is that (especially for FPGAs ) the
Synthesis tool is implementing the "mod " by using a shift register(
register width =double width of y, y loaded in the upper part of the
register) The mod is executed by "Right" Shifts equal to this
Integer(n) mentioned above (Division in binary ) and the result will be
loaded in the lower part of the register.
for example :
(12 mod 8) = 12 mod 2^^3
12 fits in 4 bits .. so the synthesis tool allocated a register of 8
bits .
12 is loaded in the upper part " 1100 0000 "
to execute the mod 8 ===> shift right "n" bits , shift right 3 bits.
then the register will hold "0001 1000" then the 3 shifted bits in the
lower part is the result which will be "100" as 12 mod 8 = 4
if we make 12 mod 16 which is 12 mod 2^^4 then it will shift right 4 the
4 shifted bits in the lower part will be 1100 exactly 12 mod 16 = 12 !
and so on ....This is as I thought of it , may be there are another
schemes of synthesis for the same function.
Now how to implement non Power of 2 numbers as your case x mod 79
you will have an option like looping a subtraction till you get the
result For example inspect this process
""
mod79(x=y mod 79) : process
begin
if y < 79 then
x =y;
else
loop
x = y - 79 ;
if x < 79 then
exit ;
end if ;
end loop;
end if ;
end process mod79(x=y mod 79);
""==============check Syntax please ..
This piece of code implement x = y mod 79
Here the Synthesis tool would use combinational logic comparators and
subtractors with feed back as i might think ..
I hope this effort to resolve your problem could be helpful...:)
Best Regards ,
Mohamed A Salem
Handasa Arabia Organization
www.handasarabia.org
VOn Wed, 2003-05-28 at 09:00, ccsin@k7mail.com wrote:
> Hi all,
>
> I am trying to convert the behavioral level coding to RTL ..
>
> But i'm facing problem with the MOD 79 Adder. Does anyone have the idea how to
> design it?
>
> I have try to synthesize with the following code:
>
> add_79 = (a+b+c+d) % 79;
>
> but the synthesizer only can deal with modulor power of 2.
>
> For the MOD 32 ADDER it's fine,i have synthesized it
>
>
> THank you for helping
>
> Best regards
>
> ----- Original Message -----
> From: ChuanChew Sin <ccsin@k... >
> To: khatib@o...
> bluetooth@o...
> Date: Fri, 23 May 2003 09:21:07 +0800
> Subject: Re: Re: Re: [bluetooth] FH Selector implementaion query...
>
> >
> >
> > Hi Khatib,
> >
> > I've already simulated the FH Selection block and i got the result
> > exactly same as the Sample data.
> >
> > I have sent you all the files,there are in your mail.
> >
> > My question is: How to implement for the Data Descrambler
> > design??Please give me some guide.Because I have done the Scrambler
> > design,and got the correct results.
> >
> > Best regards
> >
> > Chuan Chew
> >
> >
> >
> > Jamil Khatib <khatib@o... > WROTE :-
> >
> > >From : Jamil Khatib <khatib@o... >
> > TO : ChuanChew Sin <ccsin@k... >
> > CC : bluetooth@o...
> > Subject : Re: Re: [bluetooth] FH Selector implementaion query...
> >
> > Hi,
> >
> > First of all please do not send files over the mailing list send
> > them to my
> > email directly and after reviewing them we will put them on the
> > CVS.
> >
> > Second please send me the files of all other blocks.
> >
> > I'll review the files and send you my comments soon. Did you made a
> > simulation for them?
> >
> >
> > >One last question: Can you tell me how is the design for Data
> > de-scrambler??
> >
> > What do you mean?
> >
> > Regards,
> > Jamil Khatib
> >
> > On 5/22/2003, "ChuanChew Sin" <ccsin@k... > wrote:
> >
> > >
> > >
> > >
> > >
> > > ChuanChew Sin <ccsin@k... > WROTE :-
> > >
> > >>From : ChuanChew Sin <ccsin@k... >
> > >TO : ccsin@k... , anilnainwal@s...
> > >CC : Jamil Khatib <khatib@o... >,
> > bluetooth@o...
> > >Subject : Re: [bluetooth] FH Selector implementaion query...
> > >
> > >Message Follows-:
> > >
> > >Hi Anil and Jamil,
> > >
> > >Long time have not heard from you,how are you??
> > >
> > >
> > >I have finally finished the FH Selection Kernel but just for
> > 79hop
> > system.Currently i just do my verilog coding is in behavioral
> > level. I will
> > change them to RTL level one day,quite busy recently.
> > >
> > >I will send you my code and the general description to
> > you,there are total
> > 7files. please give me advices.
> > >
> > >One last question: Can you tell me how is the design for Data
> > de-scrambler??
> > >
> > >
> > >Thank you
> > >
> > >Best Regards
> > >
> > >
> > > Anil Nainwal - Sofblueindia
> > <anilnainwal@s... > WROTE :-
> > >
> > >>From : Anil Nainwal - Sofblueindia
> > <anilnainwal@s... >
> > >TO : ChuanChew Sin <ccsin@k... >
> > >CC : bluetooth@o... , Jamil Khatib
> > <khatib@o... >
> > >Subject : Re: Re: Re: CRC sample dataquestion??pls reply ASAP
> > >
> > >Message Follows-:
> > >
> > >
> > >Dear Chuan,
> > >
> > >I went through your code.
> > >
> > >The problem that I could see is:
> > >
> > >In your module crc_ccitt , You have defined output
> > [`BITS_OUT-1:0] crc_out;
> > >
> > >This means that MSB is bit 15(16th bit) and LSB is bit 0.
> > Fine..
> > >
> > >
> > >
> > >Now, UAP is 47 that is (0100 0111) with LSB on the left most
> > side i.e
> > UP0(LSB) is 0 and UP7(MSB) is 1.--------(1)
> > >
> > > Now, in both test benches, you have defined reg [`BYTE-1:0]
> > uap, this means
> > if written in a format of (ABCD EFGH) , A will be MSB and H is LSB
> > >
> > >CASE 1: Now, when you initialize uap in test bench crc_sim you
> > are
> > initializing it as
> > >
> > >uap= `BYTE'h47; ie 0100 0111
> > >
> > > it means msb (UP7) is 0 and LSB (UP0) is 1. now compare
> > it with (1)
> > and you will find it's mismatching. So here is the problem.
> > >
> > >
> > >
> > >CASE 2: When you initialize UAP in crc_sim1, what you are doing
> > is.
> > >
> > > uap= `BYTE'h2e; ie 0010 1110.
> > >
> > > This means MSB (UP7) is 0,. UP5= 1. UP1=1 and
> > LSB(UP0)=0.
> > >
> > > Now compare it again with (1) and you will find all
> > the bits are
> > mismatching.
> > >
> > >
> > >
> > >I think Similar kind of problem is there while initializing
> > others.
> > >
> > >Solution:
> > >
> > > If you have defined reg [`BYTE-1:0] uap, then
> > initialize uap as
> > (1110 0010) that comes to be E2. and not 2E.
> > >
> > > But check the same problem while initializing other
> > parameters
> > as well.
> > >
> > >
> > >
> > >Then one more solution that comes to my mind is you define reg
> > [0:`BYTE-1]
> > uap, and then initialize it as in CASE 1, ie 47 (0100 0111) this
> > will make
> > 0 as MSB and 1 as LSB. And this is same as (1), I havenot tried it
> > yet but
> > you try and then please tell me if it works.
> > >
> > >But do take care while initializing others, this is one basic
> > problem i
> > could see on first go, I will check it more. but till then you try
> > this and
> > also check that other initializations are fine.
> > >
> > >you are welcome to put your queries....
> > >
> > >If I am wrong..plz let me know.. suggestions will be
> > appreciated.
> > >
> > >Best Regards
> > >
> > >Anil Nainwal
> > >
> > >
> > >
> > >----- Original Message -----
> > >From: "ChuanChew Sin" <ccsin@k... >
> > >To: <anilnainwal@s... >
> > >Sent: Tuesday, April 29, 2003 7:31 AM
> > >Subject: Re: Re: Re: CRC sample dataquestion??pls reply ASAP
> > >
> > >
> > >> Hi Anil Nainwal,
> > >>
> > >> Sorry to bother you again.
> > >>
> > >> Have you checked the code I sent to you yesterday??I
> > really hope that you
> > could find out the problem that i'm facing right now.
> > >>
> > >> Best regards.
> > >>
> > >> Chuan Chew
> > >
> > >
> > >
> >
> --
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--
Mohamed A Salem
Handasa Arabia Organization
www.handasarabia.org
--
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