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[fpu] fasu synthesis
Just to warm everybody; here is preliminary timing analysis done by DC.
Target lib TSMC 0.25. As you can see DC put some DesignWare components
in. Current clock could be roughly 200MHz. I think fasu can work even
faster. These results are the first (I synthesied it just 5 minutes
ago). Also wait until final post-layout timing analysis results (that
will be much more accurate than this one).
--damjan
****************************************
Report : timing
-path full
-delay max
-max_paths 1
Design : fasu
Version: 1999.10
Date : Mon Jul 17 14:36:50 2000
****************************************
Operating Conditions: typical Library: typical
Wire Load Model Mode: segmented
Startpoint: opa_r_reg_29_
(rising edge-triggered flip-flop clocked by clk)
Endpoint: u0/fracta_out_reg_2_
(rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Des/Clust/Port Wire Load Model Library
------------------------------------------------
add_sub24_r TSMC25_Conservative typical
fasu TSMC25_Conservative typical
equ TSMC25_Conservative typical
equ_DW01_cmp2_8_0 TSMC25_Conservative typical
equ_DW01_sub_8_4 TSMC25_Conservative typical
equ_DW01_cmp2_24_0 TSMC25_Conservative typical
Point Incr
Path
--------------------------------------------------------------------------
clock clk (rise edge) 0.00
0.00
clock network delay (ideal) 0.00
0.00
opa_r_reg_29_/CK (DFFX4) 0.00
0.00 r
opa_r_reg_29_/Q (DFFX4) 0.31
0.31 r
u0/opa_29_ (equ) 0.00
0.31 r
u0/gt_77/B_6_ (equ_DW01_cmp2_8_0) 0.00
0.31 r
u0/gt_77/U17/Y (NAND2BX4) 0.15
0.46 r
u0/gt_77/U13/Y (AND2X4) 0.13
0.58 r
u0/gt_77/U14/Y (OAI2BB1X4) 0.04
0.62 f
u0/gt_77/U23/Y (AOI2BB2X4) 0.16
0.78 f
u0/gt_77/U11/Y (AOI2BB2X4) 0.14
0.92 r
u0/gt_77/U36/Y (BUFX16) 0.13
1.05 r
u0/gt_77/LT_LE (equ_DW01_cmp2_8_0) 0.00
1.05 r
u0/U285/Y (BUFX16) 0.12
1.18 r
u0/U598/Y (MXI2X4) 0.22
1.40 r
u0/sub_84/B_2_ (equ_DW01_sub_8_4) 0.00
1.40 r u0/sub_84/U13/Y (NAND3X4) 0.16
1.62 r
u0/sub_84/U21/Y (NAND3X4) 0.06
1.69 f
u0/sub_84/U95/Y (AOI2BB2X4) 0.13
1.81 r
u0/sub_84/U34/Y (XOR2X4) 0.30
2.11 r
u0/sub_84/DIFF_4_ (equ_DW01_sub_8_4) 0.00
2.11 r
u0/U292/Y (INVX8) 0.06
2.17 f
u0/U218/Y (NAND2X4) 0.13
2.29 r
u0/U279/Y (INVX8) 0.06
2.35 f
u0/U275/Y (BUFX12) 0.12
2.47 f
u0/U276/Y (OAI2BB1X4) 0.13
2.61 f
u0/U335/Y (CLKINVX8) 0.06
2.67 r
u0/U333/Y (NOR2X4) 0.03
2.71 f
u0/U331/Y (AOI21X2) 0.17
2.88 r
u0/U332/Y (OAI2BB1X4) 0.08
2.96 f
u0/U361/Y (AOI22X2) 0.28
3.24 r
u0/U356/Y (NAND2X4) 0.04
3.27 f
u0/U354/Y (CLKINVX8) 0.06
3.33 r
u0/U355/Y (MXI2X4) 0.12
3.45 f
u0/gt_105/A_11_ (equ_DW01_cmp2_24_0) 0.00
3.45 f
u0/gt_105/U118/Y (NAND2BX4) 0.16
3.62 r
u0/gt_105/U124/Y (NAND2X4) 0.05
3.66 f
u0/gt_105/U105/Y (INVX8) 0.07
3.73 r
u0/gt_105/U75/Y (NAND2X4) 0.04
3.77 f
u0/gt_105/U74/Y (CLKINVX8) 0.05
3.82 r
u0/gt_105/U70/Y (NAND2X4) 0.05
3.87 f
u0/gt_105/U64/Y (NOR3BX4) 0.14
4.01 r
u0/gt_105/U65/Y (NOR4X1) 0.09
4.10 f
u0/gt_105/U134/Y (OAI2BB1X4) 0.18
4.28 f
u0/gt_105/U42/Y (INVX8) 0.10
4.37 r
u0/gt_105/LT_LE (equ_DW01_cmp2_24_0) 0.00
4.37 r
u0/U585/Y (BUFX20) 0.16
4.53 r
u0/fracta_out_reg_2_/SE (SDFFX1) 0.00
4.53 r
data arrival time
4.53
clock clk (rise edge) 3.00
3.00
clock network delay (ideal) 0.00
3.00
clock uncertainty -0.38
2.62
u0/fracta_out_reg_2_/CK (SDFFX1) 0.00
2.62 r
library setup time -0.69
1.93
data required time
1.93
--------------------------------------------------------------------------
data required time
1.93
data arrival time
-4.53
--------------------------------------------------------------------------
slack (VIOLATED)
-2.60
u0/sub_84/U25/Y (NAND2X4) 0.07
1.47 f
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