Re: [pci] Problem testing PCI board

["Miha Dolenc" <mihad@opencores.org>]

Hi!

Not meeting those two constraints is nothing to worry about.
They only tell the tool that clock domain crossing signals should be as fast
as possible - you can
increase the constraints if you want.
About the card not being found - did you try
lspci command in Linux?

Regards,
Miha Dolenc

----- Original Message -----
From: "Marco Buffa" <marcobuffa@lombardiacom.it>
To: <pci@opencores.org>
Sent: Tuesday, April 01, 2003 8:18 PM
Subject: [pci] Problem testing PCI board


> Hi all,
> I've just finished my PCI board and I'm going to test it with the vga
> application.
>
> I'm using ISE 4.1 with FPGA express.
> My FPGA is a SpartanII 200 -6.
> I'm using the constrain file .../apps/crt/syn/ucf/pci_crt.ucf, changing
> the pad location constraints according with my board layout.
> During PAR, the placer can't meet 2 timing constraints:
>
> (from my log file)
> ------------------------------------------------------------------------
>    Constraint                                |Requested |  Actual  | LL
> ------------------------------------------------------------------------
> * TS_CLK_2_CRT_CLK = MAXDELAY FROM TIMEGRP  | 5.000ns  | 10.964ns | 10
>    "CLK" TO TIMEGRP "CRT_CLK" 5 nS           |          |          |
> ------------------------------------------------------------------------
> * TS_CRT_CLK_2_CLK = MAXDELAY FROM TIMEGRP  | 5.000ns  | 7.500ns  | 9
>    "CRT_CLK" TO TIMEGRP "CLK" 5 nS           |          |          |
> ------------------------------------------------------------------------
>
> I've tried a lot of syntesys/implementation options, without any result
:-(
> Readind the file .../apps/crt/syn/out/bit/fe.log I've seen that the 2
> problematic timing constraints are very different from mine:
>
> (from fe.log file)
> ------------------------------------------------------------------------
>    TS_CLK_2_CRT_CLK = MAXDELAY FROM TIMEGRP  | 30.000ns | 21.603ns | 9
>    "CLK" TO TIMEGRP "CRT_CLK" 30 nS          |          |          |
> ------------------------------------------------------------------------
>    TS_CRT_CLK_2_CLK = MAXDELAY FROM TIMEGRP  | 30.000ns | 16.423ns | 8
>    "CRT_CLK" TO TIMEGRP "CLK" 30 nS          |          |          |
> ------------------------------------------------------------------------
>
> Why?
>
> Then I've modified the file .../apps/crt/syn/ucf/pci_crt.ucf, according
> with fe.log, and I've compiled and loaded the core in the Spartan.
> Starting the PC with my board loaded and connected to the PCI bus, the
> motherboard doesn't find it on the bus, and typing the linux command
> "scanpci", I can't find my board in the list.
> Is it due to the 2 timing constraints?
>
> Sorry for the long message, can anyone explain me the ucf mismatch and
> help me with the recognising problem?
>
> Thank you.
> --
> Marco (Politecnico di Milano, Italy)
>
> "Qui se accendessero le luci e riabbassassero le luci
> ci troverebbero tutti in piedi con gli occhi aperti, qui"
> (Ivano Fossati, "Sigonella")
>
> --
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>


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