[pci] PCI bus in Quartus II 2.0??????

[klm681@mail.usask.ca]

Has anyone compiled the PCI bus IP core using Quartus II 2.0 software 
from Altera?  I tried, but I get this error message :"Unsupported Verilog 
HDL feature error: parameter value assignment in module instatiation is 
not supported".  It appears like this line is causing problems : 
WB_TPRAM #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbu_fifo_storage.  
Any ideas?  I don't really have the time to go through every module and 
correct errors...
--
To unsubscribe from pci mailing list please visit http://www.opencores.org/mailinglists.shtml