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I'm thinking along some similar lines and quite frankly, I dont really know
which nets should be critical and how critical they should be. For instance,
should FRAME, IRDY, TRDY, DEVSEL have clock to pad of 1/2 33Mhz (or about
18NS)? Should it be tighter? What other nets (and I presume we are only
talking about nets in top.v connected to the outside world should be in this
list? All of the nets except RST? Please pardon the naivety of the question,
this is really the first time I have done anything like this. (er-ahh, I'm a
software guy trying to learn how to do this magic Verilog stuff, I saw my
first Verilog program less then 6 weeks ago) [but I do now have a reset
generator, clock, arbiter and I can synthesize and implement the bridge into
an FPGA, I can even follow wires through the design now].

On the progress note, I got the XScale 80200/80312 to boot reliably with a
PCICLK generated from a system controller module, I can make my own RST,
power the device and it is connected to my VirtexE with the PCI bridge
installed. I can issue configuration accesses and see FRAME, IRDY, REQ,
CBE[3:0] all do their thing on the logic analyzer. Nothing is responding
because I dont have IDSEL connected to anything yet, but tomorrow...

Charles Krinke


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