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Re: [pci] constrain file



Thanks,

I succeed with timings.

Problem was with Synplify syn_hier attribute. When I set syn_hier = hard
{preserve hierarchy} on CRIT modules I got warnings about VCC and GND not
connected (again, just like problem with syn_netlist_hierarchy). But on
Xilinx site I founded that is Synplify optimisation problem and that we can
ignore those warnings.

Regards,

Gvozden

----- Original Message -----
From: "Tadej" <tadej@opencores.org>
To: <pci@opencores.org>
Sent: Wednesday, June 12, 2002 3:42 PM
Subject: RE: [pci] constrain file


> Hi!
>
> I assume you are using the Opencores PCI bridge.
> On the PCI side, which have high timing constraints, we put
> some logic into separate files with word "crit" in the name
> of the files. To these files (or modules) and just to these
> ones you should assign a preserve hierarchy.
> That is how they are not optimised with the rest of the logic.
> With this you should meet timings.
>
> Please respond if you will succeed or fail with timings.
>
>
> Best regards,
> Tadej
>
>
> -----Original Message-----
> From: owner-pci@opencores.org [mailto:owner-pci@opencores.org]On Behalf
> Of Pinhas.Krengel@formalized.com
> Sent: Wednesday, June 12, 2002 3:13 PM
> To: pci@opencores.org
> Subject: Re: [pci] constrain file
>
>
> Hi
> Sometimes it is just enough to tell (manual placement) the place and
> route software just a few critical modules.
> As you can see in the documentation as well as by the file name, the
> core's critical modules. Synthesize each of them separatly and manually
> place them.
> Then give it a try with a few seeds (assuming you use XILINX tools).
>
> ----- Original Message -----
> From: "Gvozden Marinkovic" <gvozden@t... >
> To: <pci@o... >
> Date: Fri, 7 Jun 2002 17:11:35 +0200
> Subject: [pci] constrain file
>
> >
> >
> > Can you send constraint file for synthesis tool (in txt format)?
> > I cannot meet timing constraints.
> >
> > Sincerely,
> >
> > Gvozden
> >
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