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[pci] model sim scripts (1.do)

To: pci@opencores.org
Subject: [pci] model sim scripts (1.do)
From: pinhas.krengel@formalized.com
Date: Mon, 15 Apr 2002 13:25:58 -0400
Reply-To: pci@opencores.org
Sender: owner-pci@opencores.org
# start recording not at the begining
run 106455000


# add wave clk
# add wave rst
# add wave fp
# add wave msk
# add wave dbg
# add wave -literal -hex lda
# add wave -literal      /u0/cntq
# add wave fpo


#DUT PCI
# vcd add /SYSTEM/bridge32_top/CLK
# vcd add /SYSTEM/bridge32_top/RST
# vcd add /SYSTEM/bridge32_top/IDSEL
# vcd add /SYSTEM/bridge32_top/FRAME
# vcd add /SYSTEM/bridge32_top/AD
# vcd add /SYSTEM/bridge32_top/CBE
# vcd add /SYSTEM/bridge32_top/IRDY
# vcd add /SYSTEM/bridge32_top/TRDY
# vcd add /SYSTEM/bridge32_top/DEVSEL
# vcd add /SYSTEM/bridge32_top/DEVSEL_in
# vcd add /SYSTEM/bridge32_top/DEVSEL_out
# vcd add /SYSTEM/bridge32_top/DEVSEL_en
# vcd add /SYSTEM/bridge32_top/my_devsel
  vcd add /SYSTEM/bridge32_top/FRAME_en
  vcd add /SYSTEM/bridge32_top/FRAME_out
  vcd add /SYSTEM/bridge32_top/PERR_out
  vcd add /SYSTEM/bridge32_top/PERR_en
  vcd add /SYSTEM/bridge32_top/PERR_in
# WB PCI master state machine
vcd add /SYSTEM/bridge32_top/bridge/wishbone_slave_unit/pci_initiator_sm/sm_address
vcd add /SYSTEM/bridge32_top/bridge/wishbone_slave_unit/pci_initiator_sm/sm_data_phases
vcd add /SYSTEM/bridge32_top/bridge/wishbone_slave_unit/pci_initiator_sm/sm_decode_count_enable
vcd add /SYSTEM/bridge32_top/bridge/wishbone_slave_unit/pci_initiator_sm/sm_idle
vcd add /SYSTEM/bridge32_top/bridge/wishbone_slave_unit/pci_initiator_sm/sm_transfer
vcd add /SYSTEM/bridge32_top/bridge/wishbone_slave_unit/pci_initiator_sm/sm_turn_arround
vcd add /SYSTEM/bridge32_top/bridge/wishbone_slave_unit/pci_initiator_sm/cur_state
vcd add /SYSTEM/bridge32_top/bridge/wishbone_slave_unit/pci_initiator_sm/reset_in
vcd add /SYSTEM/bridge32_top/bridge/wishbone_slave_unit/pci_initiator_sm/clk_in
vcd add /SYSTEM/bridge32_top/bridge/wishbone_slave_unit/pci_initiator_sm/change_state
vcd add /SYSTEM/bridge32_top/bridge/wishbone_slave_unit/pci_initiator_sm/ch_state_med
vcd add /SYSTEM/bridge32_top/bridge/wishbone_slave_unit/pci_initiator_sm/sm_data_phases
vcd add /SYSTEM/bridge32_top/bridge/wishbone_slave_unit/pci_initiator_sm/pci_trdy_in
vcd add /SYSTEM/bridge32_top/bridge/wishbone_slave_unit/pci_initiator_sm/pci_stop_in
vcd add /SYSTEM/bridge32_top/bridge/wishbone_slave_unit/pci_initiator_sm/ch_state_slow
vcd add /SYSTEM/bridge32_top/bridge/wishbone_slave_unit/pci_initiator_sm/pci_frame_out_in
vcd add /SYSTEM/bridge32_top/bridge/wishbone_slave_unit/pci_initiator_sm/mabort1
vcd add /SYSTEM/bridge32_top/bridge/wishbone_slave_unit/pci_initiator_sm/mabort2

vcd add /SYSTEM/pci_behaviorial_device1/target_debug_force_bad_par
vcd add /SYSTEM/pci_behaviorial_device1/master_debug_force_bad_par
vcd add /SYSTEM/pci_behaviorial_device2/target_debug_force_bad_par
vcd add /SYSTEM/pci_behaviorial_device2/master_debug_force_bad_par


# PCI
vcd add /SYSTEM/pci_clock
vcd add /SYSTEM/AD 
vcd add /SYSTEM/CBE 
vcd add /SYSTEM/RST 
vcd add /SYSTEM/INTA 
vcd add /SYSTEM/MAS0_REQ 
vcd add /SYSTEM/MAS0_GNT 
vcd add /SYSTEM/MAS1_REQ 
vcd add /SYSTEM/MAS1_GNT 
vcd add /SYSTEM/MAS2_REQ 
vcd add /SYSTEM/MAS2_GNT 
vcd add /SYSTEM/FRAME 
vcd add /SYSTEM/IRDY 
vcd add /SYSTEM/TAR0_IDSEL
vcd add /SYSTEM/TAR1_IDSEL
vcd add /SYSTEM/TAR2_IDSEL
vcd add /SYSTEM/DEVSEL 
vcd add /SYSTEM/TRDY 
vcd add /SYSTEM/STOP 
vcd add /SYSTEM/PAR 
vcd add /SYSTEM/PERR 
vcd add /SYSTEM/SERR 
# parity check debug
vcd add /SYSTEM/parity_checking/perr_asserted

# vcd add /SYSTEM/bridge32_top/FRAME_en
# vcd add /SYSTEM/bridge32_top/FRAME_out

# vcd add /SYSTEM/pci_behaviorial_device2/test_pad_frame/external_sig
# vcd add /SYSTEM/pci_behaviorial_device2/test_pad_frame/data_out_dly2
# vcd add /SYSTEM/pci_behaviorial_device2/test_pad_frame/data_oe_dly1
# vcd add /SYSTEM/pci_behaviorial_device2/test_pad_frame/data_oe_dly2
# vcd add /SYSTEM/pci_behaviorial_device2/test_pad_frame/force_data_x
# vcd add /SYSTEM/pci_behaviorial_device2/test_pad_frame/data_oe_comb

# vcd add /SYSTEM/pci_behaviorial_device2/pci_ext_trdy_l
# vcd add /SYSTEM/pci_behaviorial_device2/target_trdy_out
# vcd add /SYSTEM/pci_behaviorial_device2/target_d_t_s_oe



# WISHBONE slave interface
# vcd add /SYSTEM/ADR_I
# vcd add /SYSTEM/SDAT_I
# vcd add /SYSTEM/SDAT_O
# vcd add /SYSTEM/SEL_I
# vcd add /SYSTEM/CYC_I
# vcd add /SYSTEM/STB_I
# vcd add /SYSTEM/WE_I
# vcd add /SYSTEM/CAB_I
# vcd add /SYSTEM/ACK_O
# vcd add /SYSTEM/RTY_O
# vcd add /SYSTEM/ERR_O

# WISHBONE master interface
# vcd add /SYSTEM/ADR_O
# vcd add /SYSTEM/MDAT_I
# vcd add /SYSTEM/MDAT_O
# vcd add /SYSTEM/SEL_O
# vcd add /SYSTEM/CYC_O
# vcd add /SYSTEM/STB_O
# vcd add /SYSTEM/WE_O
# vcd add /SYSTEM/CAB_O
# vcd add /SYSTEM/ACK_I
# vcd add /SYSTEM/RTY_I
# vcd add /SYSTEM/ERR_I
# vcd add /SYSTEM/wb_clock
# vcd add /SYSTEM/reset_wb

#wishbone master
# vcd add /SYSTEM/wb_clock
# vcd add /SYSTEM/reset_wb
# vcd add /SYSTEM/reset

# vcd add /SYSTEM/bridge32_top/bridge/pci_resets_and_interrupts/pci_rstn_in
# vcd add /SYSTEM/bridge32_top/bridge/pci_resets_and_interrupts/conf_soft_res_in
# vcd add /SYSTEM/bridge32_top/bridge/pci_resets_and_interrupts/rst_o


# vcd add /SYSTEM/pci_behaviorial_device2/test_pad_idsel/pci_ext_clk


  run -all
# run 100000
quit


--
Best Regards,

Pinhas Krengel
Sr. ASIC / FPGA Engineer
Formalized Design Alliance Partner
011 972-9-894-7865 Home Office
011 972-54-679-119 Portable
480-545-4555 Jim McHood, VP Engineering
www.formalized.com

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