[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [pci] model sim scripts

To: pci@opencores.org
Subject: Re: [pci] model sim scripts
From: Kent Ulrich <k.ulrich@ieee.org>
Date: Mon, 15 Apr 2002 08:32:03 -0400
References: <20020414191551.FLDM25614.imta01a2.registeredsite.com@smtp.registeredsite.com>
Reply-To: pci@opencores.org
Sender: owner-pci@opencores.org
User-Agent: Mozilla/5.0 (Windows; U; Win95; en-US; rv:0.9.4) Gecko/20011128 Netscape6/6.2.1
Pinhas,
    Thanks for sharing your ModelSim scripts. Could you also show us 
your simulation dofile "1.do" also?
I've been trying to bring up the simulation with Aldec Riviera, but I 
get a lot of errors right from the beginning. Has anyone else tried to 
run the simulation with Aldec Riviera?

Kent Ulrich
k.ulrich@ieee.org


pinhas.krengel@formalized.com wrote:

>Follows scripts for model sim. Please send remarks.
>
>A few points regarding the compile script.
>1. The result are placed in the comp.log.
>2. If there are no errors or warning the file will be empty.
>3. In order to measure the compile time, I create to files:comp1.log and 
>   comp2.log .
>
>The simulation scripts allows two modes: batch and GUI. It is targeted for 
>xilinx use. It crates the files: sim1.txt and sim2.txt just to enable the 
>measure of simulation run time.
>
>del comp.log
>
>REM timescale 1ns/10ps"
>REM RTL sources
>REM by PK in order not change the original code
>echo "compile start" > comp1.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\pci_parity_check.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\pci_target_unit.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench +define+GUEST rtl\wb_addr_mux.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\cbe_en_crit.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\fifo_control.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\out_reg.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\pci_tpram.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\wb_master.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\conf_cyc_addr_dec.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\frame_crit.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\pci_target32_clk_en.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\pciw_fifo_control.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench +define+GUEST rtl\wb_slave.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench +define+GUEST rtl\conf_space.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\frame_en_crit.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\par_crit.v >> comp.log
>
>REM by PK file not supplied
>REM vlog -quiet -incr -hazards +incdir+rtl+bench rtl\pci_target32_ctrl_en_crit.v >> comp.log
>
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\pciw_pcir_fifos.v >> comp.log
>
>vlog -quiet -incr -hazards +incdir+rtl+bench +define+GUEST rtl\wb_slave_unit.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\frame_load_crit.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench +define+GUEST rtl\pci_bridge32.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\pci_target32_devs_crit.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\perr_crit.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\wbr_fifo_control.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\cur_out_reg.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\pci_decoder.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench +define+GUEST rtl\pci_target32_interface.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\perr_en_crit.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\wbw_fifo_control.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\decoder.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\pci_in_reg.v >> comp.log
>
>REM by PK file not supplied
>REM vlog -quiet -incr -hazards +incdir+rtl+bench rtl\pci_target32_load_crit.v >> comp.log
>
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\serr_crit.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\wbw_wbr_fifos.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\delayed_sync.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\irdy_out_crit.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\pci_io_mux.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\pci_io_mux_ad_en_crit.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\pci_io_mux_ad_load_crit.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\pci_target32_sm.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\serr_en_crit.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\delayed_write_reg.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\mas_ad_en_crit.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\mas_ad_load_crit.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\pci_master32_sm.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\pci_target32_stop_crit.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\synchronizer_flop.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\async_reset_flop.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\mas_ch_state_crit.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\pci_master32_sm_if.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\pci_target32_trdy_crit.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench +define+ACTIVE_LOW_OE rtl\top.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench +define+GUEST rtl\pci_rst_int.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\sync_module.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench rtl\wb_tpram.v >> comp.log
>REM Sim sources
>vlog -quiet -incr -hazards +incdir+rtl+bench bench\wb_master32.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench bench\wb_master_behavioral.v >> comp.log
>vlog -quiet       -hazards +incdir+rtl+bench +define+GUEST bench\system.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench bench\pci_blue_arbiter.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench bench\pci_bus_monitor.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench bench\pci_behaviorial_device.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench bench\pci_behaviorial_master.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench bench\pci_behaviorial_target.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench bench\wb_slave_behavioral.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench bench\wb_bus_mon.v >> comp.log
>
>REM by PK file not supplied
>REM vlog -quiet -incr -hazards +incdir+rtl+bench bench\wb_slave32.v >> comp.log
>
>vlog -quiet -incr -hazards +incdir+rtl+bench bench\pci_behavioral_iack_target.v >> comp.log
>vlog -quiet -incr -hazards +incdir+rtl+bench bench\pci_unsupported_commands_master.v >> comp.log
>REM Libs
>REM by PK mask
>REM vlog -incr -hazards lib/xilinx/lib/unisims/RAMB4_S16_S16.v
>REM vlog -incr -hazards lib/xilinx/lib/glbl/glbl.v
>REM by PK my location
>vlog -incr -hazards +incdir+rtl+bench "C:\Program Files\modelsimXE\xilinx\verilog\src\unisims\RAMB4_S16_S16.v" 
>vlog -incr -hazards +incdir+rtl+bench "C:\Program Files\modelsimXE\xilinx\verilog\src\glbl.v"
>REM originally masked 
>REM lib/artisan/art_hsdp_256x40.v
>
>echo "compile end" > comp2.log
>
>-----
>rem vsim -quiet -c -t ps -L unisims_ver glbl system -do 1.do -l mti.log
>
>set MTI_TF_LIMIT=0
>set STDOUT=mti_log
>echo start > sim1.txt
>rem BATCH
>    vsim glbl system -quiet -do 1.do -t ps -L unisims_ver -c
>rem GUI
>rem vsim glbl system -quiet -t ps -L unisims_ver 
>echo end > sim2.txt
>
>
>--
>Best Regards,
>
>Pinhas Krengel
>Sr. ASIC / FPGA Engineer
>Formalized Design Alliance Partner
>011 972-9-894-7865 Home Office
>011 972-54-679-119 Portable
>480-545-4555 Jim McHood, VP Engineering
>www.formalized.com
>
>--
>
>
>--
>To unsubscribe from pci mailing list please visit http://www.opencores.org/mailinglists.shtml
>


--
To unsubscribe from pci mailing list please visit http://www.opencores.org/mailinglists.shtml
References:
- [pci] model sim scripts
  - From: pinhas.krengel@formalized.com
Prev by Date: Re: [pci] False PERR error at wait_perr4 (race?)
Next by Date: [pci] model sim scripts (1.do)
Prev by thread: [pci] model sim scripts
Next by thread: [pci] PCI master
Index(es):
- Date
- Thread