Re: [pci] Implementing PCI Core on Spartan IIe fpga.

["Miha Dolenc" <mihad@opencores.org>]

Hello!

Final version of the core with complete testbench will be available on the
CVS sometimes this week.
We will post a message on a list when.
We are meeting 33MHz timing in Spartan2 150K -5C, with maximum clock freq.
of arround 40MHz with our crt sample application. I don't think you will
meet 66MHz in any Spartan, because we are not using any internal tri state
buffers or other "undocumented" FPGA features, except for RAM primitives.
This makes the core retargetable.
And the core is Master/Target, so some work would have to be done to use
just the target.

Regards,
Miha Dolenc

----- Original Message -----
From: George
To: pci@opencores.org
Sent: Monday, January 14, 2002 6:35 PM
Subject: [pci] Implementing PCI Core on Spartan IIe fpga.


Good morning.  I am in the process of starting a new project requiring a PCI
slave interface on a (tentatively) Spartan IIe fpga.  Before I sink a bunch
of time into testing this core, I have a couple of quick questions.  Has
anyone had success meeting 33mhz timing specs using this core on a Spartan
IIe or similar Part?  I'm greedy, so how about 66 mhz or better?  Also, how
stable is this core?  has anyone used it successfully?  I would gladly do
some work for the cause but I need to get this project working over the next
few months.   Thanks much
                George Stein.

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