RE: [openrisc] Cache Modes In ORPsoc System

["Michael Phan" <mphan@nimbuswireless.com>]

Damjan,

Sorry for not being clear.

Yes you are right, we run the same code in RTL and it behaves OK with
different cache flavors. But when we go to the LAB, running the same code
with different cache flavors then it doesn't. We have not figure out what is
happenning yet but I will keep you informed.

I will also look into timing.

Thanks

Michael Phan


-----Original Message-----
From: owner-openrisc@opencores.org
[mailto:owner-openrisc@opencores.org]On Behalf Of Damjan Lampret
Sent: Thursday, June 26, 2003 11:35 PM
To: openrisc@opencores.org
Subject: Re: [openrisc] Cache Modes In ORPsoc System


Michael,

you will need to tell more about "running into some problems". What happens?
I assume you want to run some SW code on your FPGA implementation and it
doesn't behave as expected. Well did you try to run the same code in RTL
simulation? Did you change configuration (enable IC, IMMU etc) of the FPGA
implementation and check if the software behaves the same? Also change clock
frequency to check it isn't timing problem.

If you can pin point part of the software where it doesn't behave as
expected, send me that part and I will try to run it in my RTL simulations.

regards,
Damjan

----- Original Message -----
From: <mphan@nimbuswireless.com>
To: <openrisc@opencores.org>
Sent: Thursday, June 26, 2003 11:19 AM
Subject: [openrisc] Cache Modes In ORPsoc System


> Hi Damjan,
>
> We are running into some problems when we implement the ORPsoc in
> Xilinx FPGA, we hope you can give us some hints to solve them.
>
> Here is our configuration:
> NO DATA MMU
> NO INSTRUCTION MMU
> NO DATA CACHE
> WITH INSTRUCTION CACHE ( 4 KB)
>
> But in the LAB we can only run the DC mode.
> The other three did not run: NOCACHE, IC, and ICDC.
>
> Have you seen this before.
>
> Hope you can give us some answers
>
> Thanks
> Michael Phan
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