Re: [openrisc] OpenRisc and ModelSim/Xst

[Scott Furman <sfurman@rosum.com>]

Damon Brantley wrote:

>I have been experimenting with openrisc using ModelSim from the Xilinx
>webpack.
>I have been able to successfully synthesize an openrisc connecting to a
>simple vga interface 
>and run a few simple c programs on it. 
>I did have to make a few changes to the openrisc code code for things to
>work with Model Sim 
>and Xst.
>
I have successsfully run or1200 under ncverilog and have been trying to 
get it to compile under XST, but I am having problems.  I am a newcomer 
to the ISE environment, so maybe I am doing something stupid.  Here's 
what I do:

I added all the *.v files in the or1200 directory to the project (except 
for or1200_defines.v).  Then I chose the synthesis properties dialog and 
set the verilog include path to the or1200 directory.  During 
compilation, I saw several errors about undefined modules/primitives, 
for example:

   ERROR:HDLCompilers:87 - ../../rtl/verilog/or1200/or1200_ic_ram.v line 
135 Could
   not find module/primitive 'or1200_spram_1024x32'

That would seem to imply that the source for the named module had not 
been included in the project.  Yet if I manually select 
or1200_spram_1024x32 from the project hierarchy and synthesize it, the 
log says:

    Module <or1200_spram_1024x32> compiled

So, I know that the module *is* included in the project.   Incidentally, 
I'm using ISE 5.2 with the latest service pack installed.

Any suggestions ?  Failing any suggestions, would you be willing to 
email me your project directory ?

-Scott



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