Re: [openrisc] eCos & gcc bug

["Damjan Lampret" <lampret@opencores.org>]

Scott,

did you have any problems linking data/bss to 'h00xxxxxx and code to
'hf0xxxxxx?

I tried once and it didn't work.

regards,
Damjan

----- Original Message -----
From: "Scott Furman" <sfurman@rosum.com>
To: <openrisc@opencores.org>
Sent: Friday, April 18, 2003 7:17 AM
Subject: Re: [openrisc] eCos & gcc bug


> A couple of other things I should mention if you're going to run eCos
> under ORP:
>
> I had to change the base address for Flash from 'h04xxxxxx to 'hFxxxxxxx
> in the ORP SOC verilog.  (The latter is what eCos expects, since that
> was the documented Flash base address in the ORP specification linked
> from the OpenCores web site.  As it turns out, there's good reason to
> use the latter decoding range rather than the former:  Since the SRAM is
> at 'h00xxxxxx, using 'hFxxxxxxx as the Flash address puts the two spaces
> close enough to each other so that it's possible to make immediate
> branches between them.)
>
> The eCos code expects that the UART is clocked at 1/16 the CPU clock and
> it sets the baud rate divider based on that.  You'll need to use
> configtool to change the CPU speed (and hence the UART clock speed) that
> eCos expects.
>
> -Scott
>
>
>
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