Re: [openrisc] DC query.

[Christian Melki <christian.melki@axis.com>]

Hmm.. ok

you mean like:

sh "mkdir WORK"
define_design_lib WORK -path WORK
analyze -f verilog -library WORK or1200*.v
...
current_design or1200_top
elaborate or1200_top
... ?

I just used the default synthesis script provided in the cvs.. :)
read_design.inc called from top.scr.
read_design uses read -f verilog.. so i guess i should
use analyze and elaborate then..

regards,
/Christian

On Thu, 20 Mar 2003, Damjan Lampret wrote:

> Hi Christian,
>
> do you do
>
> read -f verilog <files.v>
>
> or do you do analyze+elaborate combo?
>
> The second is the right way and the first might result in error you see.
>
> regards,
> Damjan
>
> ----- Original Message -----
> From: Christian Melki <christian.melki@axis.com>
> To: <openrisc@opencores.org>
> Sent: Thursday, March 20, 2003 2:32 AM
> Subject: [openrisc] DC query.
>
>
> > Hello ppl.
> >
> > Thought perhaps somebody could help me
> > with this trivial question.. im running an evaluation
> > version of DC ( not ultra.. unfortunately.. see if i can get one
> > ultra eval later.. ). But im getting this error message in the
> > logs.. And since i find the dc_shell very annoying without auto-
> > completion.. ( perhaps a feature that one can turn on.. )?
> > The WORK name directory path sound very much like VHDL-style
> > to me..
> >
> > Anyway.. here is the log.. any ideas?
> > Information: Building the design 'or1200_wb_biu'. (HDL-193)
> > Warning: Can't find the design 'or1200_wb_biu'
> >         in the library 'WORK'. (LBR-1)
> > Warning: Unable to resolve reference w'or1200_wb_biu' in 'or1200_top'.
> > (LINK-5)
> > Information: Building the design 'or1200_immu_top'. (HDL-193)
> > Warning: Can't find the design 'or1200_immu_top'
> >         in the library 'WORK'. (LBR-1)
> > Warning: Unable to resolve reference 'or1200_immu_top' in 'or1200_top'.
> > (LINK-5)
> > ... and so on.
> >
> > Btw. the or1200 did reach 200MHz in an unnamed .13 target without
> > any beating on the design.. But that was with Cadence BG.. and now im
> > trying to play a bit with Synopsys DC.. 200MHz WC in .13 was easy.
> >
> > regards,
> > Christian Melki

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