Re: [openrisc] OR1200 ASIC Success probabilities.

["Damjan Lampret" <lampret@opencores.org>]

Forgot to mention - implemented features also affect timing. If you remove
MMUs for example, you will get better timing.

regards,
Damjan

----- Original Message -----
From: "Christian Melki" <christian.melki@axis.com>
To: <openrisc@opencores.org>
Sent: Thursday, February 27, 2003 12:18 PM
Subject: [openrisc] OR1200 ASIC Success probabilities.


> Hello ppl.
>
> Im curious about the OR1200 ASIC synth success...
> Is there anybody out there who is successfully
> running the or1200 in 200MHz+ using a .18 6ML process
> of any kind?
> When I try to investigate where the or1200 will take me
> in synthesis by just hooking in the clock ( getting a probable
> direction tangent.. ) I get a bad slack by 1.4 on a 5ns clock
> input... 10ns is no problem of course.
> This is rather disturbing since the slack will probably
> only get worse when all the inputs and are connected and everything
> is defined correctly.. ( this is my guess. since more blocks will
> actually get synth:ed if everything is connected )
> The synthesis is done against a .18 lib using the same
> environment (configuration) that is very succesful for
> other (unnamed) large cores.
> Now im obviously no ASIC expert.. This is the first time
> ever i have synth:ed anything.. :) So any hints are
> greatly appreciated.
> Oh btw. Im using Build Gates for synthesis. :)
>
> best regards
> MScIT Stud.
> Christian Melki
> Sweden.
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