Re: [openrisc] UART Interrupts

["Damjan Lampret" <lampret@opencores.org>]

Heya !

I expect others to comment as well.

regards,
Damjan

----- Original Message -----
From: "Carlos Sánchez de La Lama" <csanchez@teisa.unican.es>
To: <openrisc@opencores.org>
Sent: Tuesday, February 11, 2003 5:29 PM
Subject: [openrisc] UART Interrupts


> Hello!
>
> I've a problem when testing a program with or1ksim. It should be
generating
> serial interrupts,but it doesn't, so I would like you to clarify a couple
of
> things:
>
> First of all, I don't understand the IRQ settings in sim.cfg. OR1000
> architecture has only two interrupt lines, unless a PIC is present, so...
is
> always a PIC present in simulator? In other case, which are the right
values
> for this? I want tick timer on low priority line (as stated on the revised
> architecture manual) and UART on high priority one.

As you might now, tick timer now has a separate exception vector and
interrupts its own exception vector. Therefore there is no more high and low
priority interrupts - just one kind of interrupts. I don't know if PIC is
always present in the or1ksim.

>
> And second, I'm having a value of 0x0c for UART register IIR. But,
according
> to my documentation, this indicates FIFOS are both disabled (bits 6 & 7
are
> equal to zero) while bit 3, that should always be 0 with FIFOS disabled,
is
> 1. How is this possible? Do UARTs simulated by or1ksim acurately model a
real
> 16450/16550?

Should be accurate to the best of my knowledge. But maybe there are some
mismatches. You can commit a patch if you fix something.

regards,
Damjan

>
> Thank you in advance.
>
> Carlos Sanchez de La Lama <csanchez@teisa.unican.es>
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