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Re: [openrisc] OR1000 16 bit instruction set

Damjan,

Memory prices are definitely cheap right now.  We have been getting 64MBit SDRAM (8 MByte) for <$1.00 each until the last month or so.  It has started going up lately though, currently $2.75.  Still, it is amazingly cheap.

How difficult will it be to take the OR1200 and add support for the 16 bit opcodes?  Is this something that was designed to drop in, or will it be a major rework of the OR1200?  Is this something those of us who want this might tackle?  Also, is it possible to scale the OR1200 back, as in removing the MMU's?  Also, does the configuration determine part number or is it just an arbitrary assignment?

Regards,
Jeff

On Thu, 2002-02-14 at 13:43, Damjan Lampret wrote: 
Hi Jeff,

it is all about demand. Right now it looks like 32-bit insn length is most
wanted, especially because of the coming 64-bit superscalar version of the
OR1K. It is also true that prices of Flash and RAM are droping some 30% or
more each year. But if there will be enough interest for 16-bit insn length,
it could become a priority.

regards,
Damjan

----- Original Message -----
From: "Jeff Hanoch" <jeff@lowrance.com>
To: <openrisc@opencores.org>
Sent: Thursday, February 14, 2002 7:54 PM
Subject: [openrisc] OR1000 16 bit instruction set


> Hi all,
>
> What is the status of the 16 bit instruction set or OR1K processors?  Is
> this no longer supported, or is this just on the back-burner until the
> OR1200 is finished?
>
> I would like to consider using the OR1K processors in actual ASICs at my
> company, but we really need a smaller, more compact opcode than the 32
> bit OR1200.  The application would most likely be low-power, low-cost,
> hand held products.  Our products have limited FLASH memory, due to
> cost, so the 16 bit instruction width would work much better for us.  We
> currently use the ARM7TDMI.
>
> Jeff
>
>
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