Re: [ethmac] MII Management - Eth DMA

[Damjan Lampret <lampret@opencores.org>]

> 
> 2. In the EthDMA code which is sent by Damjan, I also don't understand the
>    point of txcf signal (from tx ethmac to ethdma_tx). 

This signal signals to host that MAC is transmitting control frame. I simply
latch this into TX Status register.

> 
> 3. Where can I get the specification of bus architecture we'll use ?
> 

You can use any bus architecture you want. If it looks something like the one
that I use then even better. Basically I use host port (prefixed with Opb which
means On chip Peripheral Bus) to write/read registers and Dma port for
receiving/transmitting frame data (prefix Dma). I could send some timing
diagrams to the mailing list if somebody is interested? Let me know.

regards,
Damjan

PS I have attached latest version. Currently this one has one bug (frames with
length that si not multiple of 4 bytes are not handled properly (some dummy
bytes added at reception and some extra transmitted at TX )).

veth.v