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Hi, All
When I tried to simulate the rtl code provided by the
opencores website, I failed to find the following 3 source codes. Who can help
me? Thank you very much.
ethernet/sim/rtl_sim/src/glbl.v
ethernet/rtl/verilog/generic_tpram.v
ethernet/sim/rtl_sim/src/RAMB4_S16_S16.v
ethernet/sim/rtl_sim/src/art_hsdp_256x40.v
-Chun Lin
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