Re: [ecc] My Viterbi Project and Problem(help)

[ras_hi@rediffmail.com]

hi
i am a student planning to do project in viterbi decoder can u help me 
actually i have planned to do it with k=5 , can u help me in my project 
bye
rashi
----- Original Message ----- 
From: malitj@2...  
To: ecc@o...  
Date: Sat, 1 Dec 2001 05:52:55 +0100 
Subject: [ecc] My Viterbi Project and Problem(help) 

> 
> 
> Hi , 
> I am a student. I have finished my viterbi 
> project:K=7;Rate=1/2,2/3,7/8;3 bit Soft ;f(max)=11MHz. but it is 
> too 
> large (6464 Logic element in Altera's FPGA). I use Register 
> Exchange 
> methde to implement Survivor Select and Update. So I used 64 ACS 
> Unit. 
> 
> How can I do better in the decreasing area of the viterbi decoder 
> or 
> what is the problem of my decoder? 
> 
> 
> Thanks! 
> 
> Peter Ma 
> 
--
To unsubscribe from ecc mailing list please visit http://www.opencores.org/mailinglists.shtml