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[cvs-checkins] can/ ench/verilog/can_testbench.v tl/verilog/c ...



CVSROOT:	/home/oc/cvs
Module name:	can
Changes by:	mohor	03/01/16 12:36:20

Modified files:
	bench/verilog  : can_testbench.v 
	rtl/verilog    : can_bsp.v 

Log message:
	Form error supported. When receiving messages, last bit of the end-of-frame
	does not generate form error. Receiver goes to the idle mode one bit sooner.
	(CAN specification ver 2.0, part B, page 57).

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