[cvs-checkins] uart16550/rtl/verilog uart_transmitter.v uart_ ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	uart16550
Changes by:	mohor	01/12/17 15:46:53

Modified files:
	rtl/verilog    : uart_transmitter.v uart_receiver.v uart_fifo.v 

Log message:
	overrun signal was moved to separate block because many sequential lsr
	reads were preventing data from being written to rx fifo.
	underrun signal was not used and was removed from the project.

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