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[cvs-checkins] uart16550/rtl/verilog uart_regs.v

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] uart16550/rtl/verilog uart_regs.v
From: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
Date: Mon, 17 Dec 2001 11:14:48 +0100
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	uart16550
Changes by:	mohor	01/12/17 11:14:47

Modified files:
	rtl/verilog    : uart_regs.v 

Log message:
	Things related to msr register changed. After THRE IRQ occurs, and one
	character is written to the transmit fifo, the detection of the THRE bit in the
	LSR is delayed for one character time.

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