Re: [fpu] fdiv

[Rudolf Usselmann <rudi@asics.ws>]

on 8/21/00 21:01, Jamil Khatib at jamilkhatib75@yahoo.com wrote:
> 
...
> 
> Still I did not get your point.
> it seems to me either to normalize or not to normalize
> I can not make special cases

Actually you have too. I can't explain all the rules, you *do*
need to get a copy of IEEE 754 ...

>> 
...
>> OK, lets clarify terminolagy. When you say
>> "extended" format
>> I'm thinking of 64+ bit floating point.
> 
> this is called the double precision

right.

> 
>> 
>> Every block need to do rounding. The output of the
>> add/sub
>> unit before rounding and normalization is 27 bits.
>> (one hidden
>> bit, 23 bits fraction, 3 extra bits for precision to
>> do rounding).
> 
> as far as I know the minimum extended number of bits
> that should be supported by IEEE is 32 bit for
> fraction including the hidden bit  and 11 bit for
> exponent

Sorry, you are absolutely wrong here.

> 
> OK but we will have more hardware

right, we will optimize once we will have functionally correct
code.

> are you sure in VHDL there is also some differences
> thats why I am asking

yes, I am sure.

> 
> to start from a defined state

There are no states in the fpu cores.
It's a data path engine ...
 
> OK in the next release we should start from the
> documentation to get more effecient design without
> duplication and confusions

The only person who is confused is you. The duplication is
a safety margin ...
Besides there are already too many documents. You have written
some, I have written some, what else do you need ?

>> 
>> No, probably not. I'm working on add/sub - trying to
>> figure out
>> rounding.
>> 
>> 
> 
> so let me know the results

ok


>> 
>> rudi
>> 
> 
> Jamil
> 

rudi