Re: [fpu] fdiv

[Jamil Khatib <jamilkhatib75@yahoo.com>]

Hi,

--- Rudolf Usselmann <rudi@inet.co.th> wrote:
> 
> > hi all,
> > 
> > I attached to teh email teh fdiv core it is not
> yet
> > ready there are some bugs and things to be covered
> but
> > I want your comments on teh code since it is my
> first
> > verilog code.
> 
> You must also do rounding and post normalisation.
> 

I think we discussed about the post and pre
normalization long time ago. I suggest to make the
post normalization a configurable feature in the core.

About rounding I thought that there should be a
seperate block to perform the rounding unless you mean
teh conversion from the extended format to the single
one?

> In Verilog, all sequential assignments should be non
> blocking,
> and I would recommend a 1 time unit delay for them
> as well. This
> is because some simulators might enter race
> conditions if you
> don't do this. So all sequential assignment should
> look something
> like:
> 
> always @(posedge clk)
>     Q <= #1 D;

In fact this is the most difficult part of verilog I
leanred, still I do not know what are the differences
between #1, = , and <= operators, I think they are
like signals and variable assignments in VHDL.

anyhow there are some signals that I want them to be
assigned at the moment not on teh next simulation time

> 
> 
> > Could you please let me know what the interfaces
> of
> > the other cores so as to make it compatible with
> them.
> 
> There is no need for a reset.
> 
> input           clk;
> input [31:0]    opa, opb;
> output [31:0]   out;
> output          div_zero, overflow, underflow,
> inexact, snan;
> output          "whatever other exception you can
> detect";
> 

what about teh extended format you used?, in my code I
am using 32 bit for fraction and 11 bit for exponent


> > 
> > Regards
> > Jamil Khatib
> 
> rudi
> 

Sorry for the VHDL like code I am still a beginner

Regards
Jamil Khatib


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