RE: [fpu] FPU operations

[Jamil Khatib <jamilkhatib75@yahoo.com>]

Hi all,

> >
> > > 6. I think we should provide SNAN when NAN is
> one of
> > > the comparison operands but also we should
> produce
> > > false for this kind of operation. This is even
> if the
> > > standard does not requier it but it will give
> the
> > > software more control.
> > > I don't know. Instead I have a question. Who
> decides what kind of NAN
> >is produced - QNAN or SNAN. Is this set in FP
> control register or is
> >there some kind of protocol in stanard for this?
> Maybe different FP
> >insns?
> 
> The standard only specifies that there should be
> definite values for
> both Q and S NAN. But it does not specify exactly
> how to distinguish.
> A semi-standard has evolved (based on Intel
> implementations):
> SNAN has highest bit (bit 22) in the fraction
> (mantissa) section set,
> and QNAN has it cleared.
> 

I got your points from the previous email, So we
should not provide SNAN upon comparisons with NAN
operands.

> >
> >BTW since Rudi is working on its own and Jamil on
> its own FPU. How
> >about more closer development where both FPU would
> be basically the
> >same except of the HDL used. This way there would
> be one document, one
> >'C' (or Java) test vector generator, easier to fix
> bugs etc. And more
> >team spirit !
> 
> That doesn't make any sense. There should be one
> implementation only, you
> can do easy (perhaps soon automatic) translations
> between languages.
> 

I saw a translater but it is not so effecient and
anyhow teh result code must be manually modified.

> Since Jamil is always doing his own thing, and was
> on the project before
> me, I'll stop working on my cores, and let Jamil
> build them. 

In fact I am not working alone I try to ask and
provide some comments to compile them in a document
and implement the design in the most effecient way. we
need always to get comments and suggestions from
everyone.
I am trying to describe my ideas and put them in VHDL,
I tried always to get comments on my general design
block diagrams, flow charts and documents so as to
reach to a common design for everyone. you can do the
design in Verilog me in VHDL and may be another in
schematic!! but we have to reach to a common design no
matter how it is implemented.

I was waiting for your codes and descriptions but you
did not inform us about your work status. for example
I do not know that you have a c progam to generate teh
test vectors (also you did not provide the source).

Also when I decided to code the Adder block in VHDL I
did it for few reasons:
1. Your adder was not complete and you did not mention
that you are fixing it before this week.
2. even If you provided your design structure I'll
also recoded it in VHDL just to have a complete VHDL
core.
3. when I started I did not get any comment from you
on it. even if it is written in VHDL, I provided
documentation about it. me also do not know verilog
but I tried to read your code to know how to implement
my VHDL code.


Note: Open Projects do not need some one to dominate
but the design must dominate, so we have to work for
the design not for the designers.



I have some
> other ideas I'd like to follow anyway and I didn't
> fit in to this specific
> working environment anyway. Watch the main mailing
> list for some cool things
> to come !!!!  Just make sure the OR1K will be build,
> I'll need it in my
> next project !!!!
> 
> >--damjan
> 
> I'll stay in the list for another week or two, in
> case I can help with any
> questions. But will definitely sign off after that

We will be glad if you can stay with us untill we
(all) finish the FPU project


Regards
Jamil Khatib


> 
> Cheers,
> rudi
> 


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