[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [usb] Please help with a USB DPLL





----- Original Message ----- 
From: mdennis97@h...  
To: usb@o...  
Date: Sat, 17 May 2003 15:15:50 -0100 
Subject: Re: [usb] Please help with a USB DPLL 

> 
> 
> hi, Mr. rudi: 
> 
> There is another doubt about the the signal souce of RxEn_i in 
> usb_rx_phy module. In the phy top module, this signal is connected 
> to 
> txoe of usb_tx_phy. This txoe, however, if 1, means transmit in 
> process, 
> if 0, means receiving. At the same time, the clock phase lock 
> control 
> signal will only function during the receiving period. And this 
> phase lock 
> need a "1" to drive the DPLL state machine and the Find Sync 
> Pattern 
> FSM.I am afraid whether this txoe should be negatived before 
> connected to usb_rx_phy. 
>

Sorry, I made a mistake. There is no connection bugs.
 
> Regards 
> 
> Dennis 
> 
>
--
To unsubscribe from usb mailing list please visit http://www.opencores.org/mailinglists.shtml