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[usb] need TOP-Level for your USB 1.1 phy and func core
Hallo Rudi,
I 'm a VHDL developer and not familiar with verilog. I have tested
your usb 1.1 cores with my own development board with Spartan2
200 and Philips USBP11A, but it doesn't works.
Can you help me please and send a verilog top level (from your test
with XESS board??) with only EP0, EP1, EP2?
I would test the core and compare results with a comercial project
(with CYPRESS CY7C68013).
With Thanks
Martin
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