[usb] RXValid signal

["Luis J. Perez" <luis.perez@ds2.es>]

Hello everybody,

If anyone can help me, I have some questions about RXValid signal of USB
2.0 Transceiver.

1) In USB Trans spec (page 21) explains that "Each time 8 stuffed bits
are accumulated the state machine will enter the RX Data Wait state,
negating RXValid thus skipping a byte time". My questions:
- A bit stuff error supposes that after 6 ones in NRZ there is another
one (not a cero as supossed if well stuffed) ???
- "8 stuffed bits" means consecutive bits? 
- This 8 stuffed bits would be a NRZ = 111111 0 111111 0 111111 0 111111
0 ... until 8 zeros ... ?

2) The assertion of RXValid differs in HS and FS modes. For HS is
explained in Figure 5 of referred specs (CLK could be 30 or 60 MHz).
- For FS would be like this?: CLK=48MHz --> RXValid is only asserted
during 1st cycle of the 32 for each byte, isn't it?
- So, for FS mode, RXValid must be negated just after cahnging to RX
Data state in the FSM of Figure 6 (Transceiver specs).

3) About Figure 6:
- It must work @ 48 MHz (FS) or 30-60 MHz (HS), just the CLOCKOUT, isn't
it?
- What does the "!Data" mean? Does it mean the hold register is not
full? There is a stuffed bit?

Well, I think that's enough for the first time I write to the list.

As you have seen, I'm designing a transceiver in FS mode to use it with
the USB 2.0 core of OPENCORES. This will help me (making some little
changes to do a HS mode model) to test this core (I wish). If anyone
needs help...

Thanks,


========================================================
Luis Jose Perez Lafuente      	luis.perez@ds2.es
Design Engineer
Digital Design Department

Design of Systems on Silicon  	http://www.ds2.es
Av. Charles Robert Darwin, 2  	Phone.  +34-96-136 60 04
Parc Tecnologic	              	                Ext. 152
46980 Paterna (VALENCIA)      	FAX     +34-96-136 62 50
SPAIN
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