[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [pci] are there any statements in VHDL which can be used toaccess signals in sub entity

On Wed, 19 Feb 2003, wuyunsheng wrote:

> to monitor the pci bus, we must use signals in submodule. in verilog we can do this as follows(taken from system.v):
>
> wire devsel_t_s_oe = `PCI_BRIDGE_INSTANCE.DEVSEL_en && `PCI_BRIDGE_INSTANCE.TRDY_en && `PCI_BRIDGE_INSTANCE.STOP_en ;
>
> i wonder if there are any similar statements in VHDL which can be used to access signals in sub entity.

AFAIK there is no way.

In Modelsim there is a special package for this purpose, I don't know of
other software with such capabilities.

Sehr Wus,
- Matthias

-- 
                    "To get control over people, make them trust you.
                                            To make people trust you
                      don't try to tell them the truth about history
                 but make happen what you told them about the future."


--
To unsubscribe from pci mailing list please visit http://www.opencores.org/mailinglists.shtml