Re: [pci] PCI core in VHDL and PCI bursts

["Miha Dolenc" <mihad@opencores.org>]

Hello!

First regarding the VHDL version - it is not available yet and I don't know
whether any work is being done regarding that.
You should probably contact the person which posted the original message.

Regarding Read bursts:
CAB_I signal should be used concurrently with CYC_I signal, not STB_I
signal.
If you intend to burst read, you should put CYC_I and CAB_I to 1
simultaneously, while STB_I is used for
bus throttling.
I'll have to take a look into code regarding your other question when I have
some time.

Regards,
Miha Dolenc

----- Original Message -----
From: "Nico Weling" <eedniwe@granus165.eed.ericsson.se>
To: <pci@opencores.org>
Sent: Tuesday, February 18, 2003 11:11 AM
Subject: [pci] PCI core in VHDL


> Hi all,
>
> I just read this 'old' message:
>
> *************************************************************************
> On Wed, 15 May 2002, you wrote:
> > Hi Miha & Tadej -
> >
> > I have been looking at your PCI core... I noticed that it is in Verilog.
Do
> > you have a similar core in VHDL?
> > If not, I would be willing to translate it to VHDL and provide it to
> > OpenCores.
> >
> > What do you think?
> >
> > Thanks!
> > - Sundar
> **************************************************************************
>
> Does this PCI-core exist in VHDL now?
>
> Thanks in advance.
>
> Best regards,
>
> Nico.
>
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