[pci] Can read config, cannot write config (yet)

["Charles Krinke" <ckrinke@pulselink.net>]

Hello all, I have gotten my project where I can synthesize the PCI bridge
into a VirtexE and read configuration space reliably. I can both see the
address/data phases with the correct data on my logic analyzer and I can see
them from the host side of the PCI interface. Thats for reading
configuration space. The bridge is implemented as a GUEST. Now comes the
curious part. I can see that when I issue a configuration write, that the
logic analyzer shows what looks like the proper command for writing 0x1011.
And I can see the 32 bit data. The write completes successfully with no
master/target abort. The unfortunate thing is that when I read a few seconds
later, what I see on the bus and what the host receives on its command line
is the same contents that were in the command register before. So, I have
yet to figure out how to write to configutation space with the PCI_BRIDGE.
In reading the specification, it seems to me that in GUEST mode, the master
talking to the PCI_BRIDGE should be able to write both the command register
(to enable memory space and bus mastering) and to write BAR’s, but alas, I
dont quite get it yet.

As usual, any suggestions or criticisms are greatly appreciated. At least
progress is being made.

Charles Krinke


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