[pci] HOST vs GUEST

[cfk <cfk@pacbell.net>]

Since I don't seem to yet grok the HOST vs GUEST concept in the PCI Bridge
Core, I went back this morning and read the "PCI IP Core Design Document"
more carefully. When I get to paragraph 2.3.1, I see two mutually exclusive
statements. The first one says: 'If the PCI bridge is implemented as HOST,
then RW is provided for WB acesses, but RO for PCI accesses". The second one
says "If the PCI bridge is implemented as GUEST then RW is provided for PCI
target unit and RO for WB accesses".

Maybe I am getting caught up in semantics a bit here. What I need to be able
to do is perform RW to both sides of the bridge. I can accept some
constraints on either timing, mutual exclusivity, or addresses. Basically, I
need to be able to perceive the PCI bridge as a way to read and write(RW)
from the PCI bus it is connected to and have those reads and writes
translated into reads and writes on the WB bus to some other WB compatible
core (lets pick the gpio as the simplest one for now). Similarly, I need to
be able to have the WB side of this same core accept some asychronous event
(as described in the gpio core, for instance) and have that event translate
back into some memory write to the PCI bridge on the WB side and become a
memory write on the PCI device where the PCI bridge acts as a bus master
long enough to request the bus from the yet to be created arbiter and write
1 or more memory locations.

So, my question is, "Am I perceiving the capability of the PCI bridge core
correctly or incorrectly and am I getting too hung up on HOST versus GUEST
semantics in the PCI IP Core Design Document?

Charles Krinke


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