Re: [pci] Clock Domain Issues

["Jim Dempsey" <tapedisk@ameritech.net>]

Were your two clocks in phase with an underlaying 11MHz frequency?
If so, then the clocks were not completely independant. A good test
would be to run them slightly out of phase with each other

    3 x 11.001 and 2 x 10.999

Jim
----- Original Message -----
From: "Miha Dolenc" <mihad@opencores.org>
To: <pci@opencores.org>
Sent: Monday, April 29, 2002 3:56 AM
Subject: Re: [pci] Clock Domain Issues


> We ran it at 33MHz on PCI side and 22MHz on the other and it ran for a few
> days with no problems.
> The target was used mainly for configuration, master was actually
> transferring the data.
> Have you tried tightening the constraints and recompile the core?
>
> Example:
>
> TIMESPEC "TS_CLK_2_CLK2" = FROM : "CLK"     : TO : "CLK2" : 5 ;
> TIMESPEC "TS_CLK2_2_CLK" = FROM : "CLK2" : TO :  "CLK"     : 5 ;
>
> where CLK would be PCI clock and CLK2 WISHBONE clock. These go into ucf
> file.
>
> Regards,
> Miha Dolenc
>
> ----- Original Message -----
> From: "Dave Kroetsch" <dkroetsch@videolocus.com>
> To: <pci@opencores.org>
> Sent: Friday, April 26, 2002 5:41 PM
> Subject: [pci] Clock Domain Issues
>
>
> > Has anyone been successful in running the PCI core with the PCI side
> > running at one clock and the wishbone running off another?  I have tried
> > running the PCI side at 33MHz and the wishbone side at various
> > frequencies ranging from 6MHz to 60MHz, and I'm running into problems.
> >
> > I'm only testing the PCI target right now (as a guest in a PC system),
> > and I'm using the OpenCore DMA  register file as a target.  (I have also
> > tried my own register as a target) I've brought some of the wishbone
> > signals (including cyc, ack, we, stb...) out so I can scope them.  The
> > tests I have tried include:
> > 1) Writing single words
> > 2) reading single words
> > 3) writing bursts of 2 words
> > 4) writing bursts in the pattern 1-2-1
> >
> > I'm having problems with the PCI bridge generating improper wishbone
> > accesses and even hanging the PC!  This is being implemented on a
> > Xilinx Virtex2 FPGA in a PC running linux.
> >
> > Some of the symptoms include:
> > 1) The OpenCore PCI Bridge will generate extra wishbone
> >                  transactions.  eg. a PCI write of 4 words will
sometimes
> >                  work properly and sometimes generate 5 or 6 word writes
> >                  on the wishbone bus.
> >
> > 2) The bridge will enter a state where NO transactions from
> >                  the PCI side will even make it across to the wishbone
> bus,
> >                  and the transactions eventually time out
> >
> > 3) The bridge will hang, such that wishbone transactions are
> >                  CONSTANTLY being initiated and no finishing (despite
the
> >                  fact that they are being ACKed repeatedly)
> >
> >             4) The bridge enters a state where it ends EVERY attempted
> >                   transaction with a PCI STOPn and never asserts TRDYn.
> >                   This never allows the transaction to succeed.  The PC
> >                   continuously retries until a watchdog kicks, and it
> reboots.
> >
> > If I run the wishbone side at the PCI_CLK, this all seems to go away.
It
> > would seem there is a problem with the clock domain crossing.  Can
> > anyone provide any insight?
> >
> > Thanks,
> > Dave Kroetsch
> >              dkroetsch@videolocus.com
> > --
> > To unsubscribe from pci mailing list please visit
> http://www.opencores.org/mailinglists.shtml
> >
>
>
> --
> To unsubscribe from pci mailing list please visit
http://www.opencores.org/mailinglists.shtml
>

--
To unsubscribe from pci mailing list please visit http://www.opencores.org/mailinglists.shtml