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[pci] burst data phase.





pci gurus,
       I have devoleped pci 32 bit 33 mhz core with single data phase 
transaction facility only. I would like to add the burst data phases 
feature. I am devoleping that. But i strucked at one point.
How master come to know that for how many clock cycles to maintain frame. 
Any body can give me suggestions.
All kinds of suggestions are appreciated.

thanks in advance

ramu

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