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Re: [pci] PCI target
Yup, PCILOGIC only seems to connect to IRDY & TRDY.
I guess for parity we will have to manually build a xor carry chain macro.
Mikej
----- Original Message -----
From: "Miha Dolenc" <mihad@opencores.org>
To: <pci@opencores.org>
Sent: Sunday, September 02, 2001 10:23 AM
Subject: Re: [pci] PCI target
> Hi again,
>
> now, I would call that cheating ;-) . But there are still some issues
> that remain - this PCILOGIC block seems to control only clock enable
signal
> depending on the state of IRDY and TRDY signals. But there are other
signals
> that don't have any relationship to IRDY and TRDY handshaking - for
example
> address phase ( no IRDY nor TRDY are asserted then ) and PAR and incoming
> byte enables for target reads and so on. I'm having problems here too,
> because let's say some external master is doing a read through a target
> interface. I have to calculate PAR from incoming CBE signals (7ns
> constraint) and outgoing data that target is driving. Here PCI logic block
> doesn't help if I'm not mistaking?
>
> Regards,
> Miha
>
> ----- Original Message -----
> From: "MikeJ" <mikej@freeuk.com>
> To: <pci@opencores.org>
> Sent: Sunday, September 02, 2001 2:00 AM
> Subject: Re: [pci] PCI target
>
>
> > Hi Miha,
> > I am aware of these extra virtex resources, but Xilinx make no official
> > mention of it.
> > I suspect it is used to cheat a bit and meet timing in their core as you
> > say. It would be difficult for us to copy that I think.
> >
> > Mike
> >
> >
> > ----- Original Message -----
> > From: "Duane Clark" <dclark@leewardfpga.com>
> > To: <pci@opencores.org>
> > Sent: Saturday, September 01, 2001 4:41 PM
> > Subject: Re: [pci] PCI target
> >
> >
> > > Miha Dolenc wrote:
> > >
> > > > Hi all,
> > > > it's been a while since we last talked here!
> > > >
> > > > In fact, I did PCI master already and I'm resolving problems
regarding
> > > > timing for three weeks now. It's the problem that Duane is talking
> > about - I
> > > > want it generic and therefore problematic ;-( . I don't know
anything
> > about
> > > > PCILOGIC yet - I will try and find it on the internet. Duane - do
you
> > know
> > > > if this PCILOGIC block can be force used by specifying some
> constraints.
> > If
> > > > so - is this user, synthesys or physical constraint?
> > > > Some syntax example would be nice also ;-) .
> > > >
> > > > Thanx for your interest!
> > > >
> > >
> > >
> > > It is a Xilinx primitive that you instantiate. Xilinx does not mention
> > > it in their library guide, but if you look at a Virtex or Spartan II
> > > chip with fpga_editor, look along the left and right sides, near the
> > > pins, about half way up. It is a very small block with six pins, so
look
> > > carefully! There you will see a special block with dedicated wiring to
a
> > > bunch of the IO blocks, and if you click on it, you will see that it
is
> > > called PCILOGIC, along with the pin names.
> > >
> > > I figured out what was in it by instantiating it into a small test
> > > design as a black box, then doing synthesis and place and route. Then
I
> > > ran ngd2vhd, and the result was a VHDL model of the PCILOGIC. It turns
> > > out to be simple combinatorial logic. The key feature is the dedicated
> > > routing resources it has. The logic is something like this:
> > >
> > > entity pcilogic is
> > > port(
> > > IRDY :in std_logic;
> > > TRDY :in std_logic;
> > > I1 :in std_logic';
> > > I2 :in std_logic;
> > > I3 :in std_logic;
> > > PCI_CE :out std_logic
> > > );
> > > end entity pcilogic;
> > >
> > > architecture primitive of pcilogic is
> > > signal nand_irdy: std_logic := '1';
> > > signal nand_trdy: std_logic := '1';
> > > begin
> > > nand_irdy <= not IRDY nand not I1;
> > > nand_trdy <= not TRDY nand not I3;
> > > PCI_CE <= not ((not I2) and nand_irdy and nand_trdy);
> > > end architecture primitive;
> > >
> > > The I1, I2, and I3 pins are controlled depending on whether you are
> > >
> > > currently acting as a master or target.
> > >
> > >
> > > Duane
> > >
> > >
> > >
> > >
> > > --
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> > >
> > >
> >
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