Re: [pci] Question about PCI 2.2 Spec

["Miha Dolenc" <mihad@opencores.org>]

I hope this will help a bit!

----- Original Message -----
From: "llbutcher" <llbutcher@veriomail.com>
To: <pci@opencores.org>
Sent: Wednesday, June 13, 2001 10:54 AM
Subject: [pci] Question about PCI 2.2 Spec


> Anyone want to help me try to understand an obscure detail of
> the PCI spec?
>
> Assume that you have a Target Interface.  That interface sees
> a read, and ends it with retry because it should be serviced as
> a delayed read.
>
> Now assume that a Config Reference comes in and turns off
> Target Mode.
>
> After a while, Target Mode is turned back on with another Config
> Write.
>
> Should the Delayed Read in progress be ditched when the Config
> bit tirhs off target references, or should it be placed into suspended
> animation and restarted when the Target is re-enabled.
>

Delayed Read Request can be ditched at any time. The problem is, if you
already have a delayed read completion e.g. read finished on other side of
the bridge but not finished on PCI yet . I would say something like this:
If target is disabled while Read Request is present - ditch Read Request.
If target is disabled while Read Completion is present - completions may not
be ditched at any time, but specification says that if Read is not retried
within 2^^16 clock cycles, you must ditch it. So you could count cycles
while Read Completion is present regardles of Target being enabled or not.
If a read is retried in time you provide stored data, otherwise completion
will time-out and be discarded.
What do you think?

> If it is suspended and restarted, what can the PCI Configuration
> Master do totally shut down the target, to make sure that it starts
> from scratch.
>

RESET ;-)

>
> Similar question for the Master.  Assume that the Master starts a
> PCI reference which partially completes, then gets a Retry.
>
> Now the Master Enable bit in the Config Register is turned off.
>
> Should the Burst be remembered, to be completed when the
> Master is enabled later?  Or should it be ditched?  (This might
> result in a Target hang and Delayed Read Timeout much later,
> another bad thing.)
>

I would say, that master must complete all initiated transactions. So, if
master mode is turned off, it goes for new requests only - accepted Posted
Writes or Partial Reads must be completed before Master is suspended. What I
mean by this: PCI master interface doesn't care about Master Enable bit -
it's just performing posted writes and partial reads that have been retried
as normal. Master Enable bit would be relevant for oposite side - when
master is disabled, all subsequent requests are denied.
I'm not sure about this though. Have you tried asking this question on
PCISIG forum?

> If the Master is suspended and restarted, what can the Configuration
> Master do to totally punt all PCI Master Activity?
>
> Can anyone help me out by quoting the PCI version 2.2 Section
> Number which addresses this issue?
>
> Thanks:
>
> Blue Beaver
>
>
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