Re: [pci] Re: Config Space

["Miha Dolenc" <mihad@opencores.org>]

Hello!

    About your question:
If I understood you well, we are talking about access to extended
configuration space when the bridge is configured as Host (WISHBONE is host
bus in a system). WISHBONE processor will take full responsibility of
configuring the bridge and any other device residing on PCI bus. WISHBONE
conf space BA is fixed and cannot be changed, while PCI BA must be set (by
WISHBONE processor) to provide Read Only Access for conf space to PCI agents
on certain address (default is 0x00000000). As it is, we didn't think of
disabling this read only access to conf space.
Maybe - we could implement Address mask register for Configuration space
too.
All bits, except bit 31 (enable bit) would be fixed, and Read Only access
could be disabled by software if it wrote a value of 0 to this bit. By that,
read only access for opposite side of the bridge would be disabled. (That
would go for Host as well as Guest bridges).

What do you think? Are we even talking about the same thing ;-) ?

Have fun,
        Miha Dolenc

----- Original Message -----
From: "Oliver Amft" <oam@gmx.net>
To: <pci@opencores.org>
Cc: <tadej@opencores.org>
Sent: Monday, May 28, 2001 7:01 PM
Subject: [pci] Re: Config Space


> Tadej
>
> Yes, you're perfectly right with the BIOS/driver job distinction. But
let's
> consider this: The bridge is implemented into a PCI host device (no guest
> bridge anymore) and configuration is done via Wishbone. I'm just wondering
which
> requirements we're handling to software and/or to the system designer to
> configure the bridges extended config space base address; should the
registers
> be visible at all? Maybe you have an idea ready for that, please let me
know.
>
> Cheers,
> Oliver
>
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