[pci] Advice needed!

["Miha" <mihaPCI@email.si>]

Hi everyone,

   as I said, me and Tadej are working on a specification for PCI bridge.
The first problem we encountered is that block transfers on WISHBONE bus
don't guarantee serial addressing between data cycles, so we cannot consider
them as bursts. Bursts are very important for PCI (for system performance),
so I wrote an email to author of WISHBONE bus specification about this
issue. Let's hope we can work something out.
The second problem are images: all PCI bridges provide two or more images of
PCI bus address space for local processors (image is defined by base address
and address mask or block size). This images must be dynamic to allow
software to do address space mapping as it likes. So the problem is: what if
two or more immages overlap (some addresses fall into two or more image
ranges at the same time)? Does this issue have to be resolved in hardware or
hardware isn't responsible for slopy programming? Does anyone have an answer
for this? Some bridges implement different chip selects for different images
while WHISBONE specification doesn't define chip selects.

Regards,
    Miha