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Re: [openrisc] Understanding traffic cop



One other thing I noticed.
Following the example xsv_fpga_top.v, I set my unused targets to set bus
error to 1. 
The problem is that it looks like t18_ch_lower is propogating that bus
error all the 
way back to the cpu so it execptions with a bus error as well. This happens
even though my 
unused target is not selected. 
I do not see where in the code that the propogation is stopped. Obviously
this is not a problem 
with the xess project or nothing would work. 
Any suggestions on where I should look would be appreciated.

Thanks,
Damon

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