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Re: [openrisc] about cache scheme

To: openrisc@opencores.org, "zhustudio" <zhustudio@ict.ac.cn>, "openrisc@opencores.org" <openrisc@opencores.org>
Subject: Re: [openrisc] about cache scheme
From: Marko Mlinar <markom@opencores.org>
Date: Thu, 26 Jun 2003 07:59:13 +0200
In-Reply-To: <200306260330.h5Q3UQsC017397@www.opencores.org>
References: <200306260330.h5Q3UQsC017397@www.opencores.org>
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On Thursday 26 June 2003 03:31, zhustudio wrote:
> hi all,
>
> i have find if you enable cache in compile stage, and then sim in or1200
> soc platform, the instruction cache is enabled between 63400ns, and the
> instruction is l.mtspr r0,r10,0x11,  diassemble is 0xc0005011. i have test
> many programs that are provided in sw directory. so can anyone tell me why
> perform this sheme? is it a program compiler option or others. thank you
If I understood you correctly, you are referring to bit in the SR, which 
allows you to enable/disable cache. All CPUs have this functionality.
This instruction is usually specified in your loader program, e.g. reset.S

Marko


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References:
- [openrisc] about cache scheme
  - From: "zhustudio" <zhustudio@ict.ac.cn>

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