Re: [openrisc] WB:RISC Clock Ratios

["zhustudio" <zhustudio@ict.ac.cn>]

Dear Brian Adams,

The WB bus is design from WB REV.B2, so it only support synchronous 
mode, but not the Advanced Synchronous mode that define in WB REV.B3.
so it is only run half or below half of the cpu frequency.

Email: zhustudio@ict.ac.cn
Date: 2003-04-19

======= 2003-06-25 11:51:00 =======

>Hello All,
>
>  I have a (hopefully) quick sanity check to ask. For the SOC we are
>designing we want to have the ability to run WB:RISC clock ratios of 1:1
>or 1:2.  To do this I would have to (?)
>
>1) Define OR1200_CLKDIV_2_SUPPORTED
>2) Drive clmode_i on or1200_top appropriately (we plan to use an
>external switch or jumper)
>3) Drive iwb_clk_i and dwb_clk_i with either the full or half rate WB
>clock (depending on how we set #2)
>
>  Also, are there restrictions on the 1:2 WB/RISC clock relationships?
>ie. Must the WB clock must be EXACTLY 1/2 the RISC clock, and phase
>aligned.  We plan to have both, but I was wondering if either was
>absolutely necessary.
>
> I it appears that OR1200_CLKDIV_2_SUPPORTED, OR1200_CLKDIV_4_SUPPORTED
>and clmode were added to make it easy to do just what I have proposed,
>but I have been wrong before. =)
> 
>Thanks,
>Brian
>
>
>
>
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