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[openrisc] Bugs detected on or1ksim



Hello,

I've detected some bugs on or1ksim:

    (1) UART launches timeout interrupts even when receiver FIFO is
    empty. This disagrees with 16550 specification as far as i know.
    
    (2) PICSR bits don't do back to 0 when interrupt line is deasserted.
    I think it should, as the Architecture Manual says "Bits in PCSR
    represent the status of the interrupt inputs and the actual
    interrupt must be cleared in the device, which is the source of the
    interrupt".
    
A fixed version of or1ksim is available for download at UC OpenRISC
Project Web Site (http://www.teisa.unican.es/~csanchez), but I can send
patches to fix version on CVS if wanted.

Best regards!

	Carlos Sanchez de La Lama <csanchez@teisa.unican.es>


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