Re: [openrisc] Running slower wishone interfaces

["Damjan Lampret" <lampret@opencores.org>]

Mike,

I have found what is the problem. It is related to ifdefs, specifically how
OR1200_CLKDIV_2_SUPPORTED and OR1200_CLKDIV_4_SUPPORTED enable logic for 1:2
or 1:4 WB to RISC clock ratios. The problem was that by default
OR1200_CLKDIV_4_SUPPORTED was always commented in or1200_defines.v and
OR1200_CLKDIV_2_SUPPORTED was always enabled. Unfortunately logic enabled by
both defines was nested in or1200_wb_biu.v in such a way that
OR1200_CLKDIV_4_SUPPORTED when disabled also removed logic for 1:2 ratio. So
I change the nesting and now everything is OK. I have also updated
description of both defines in or1200_defines.v so that now is perfectly
clear how they need to be defined. And clmode port is still the one that
actually selects the ration (assuming the logic is enabled with
OR1200_CLKDIV_x_SUPPORTED in first place).
When testing ratios both CLKDIV defines were enabled and this never revealed
the ifdefs nesting problem. Since then ratio 1:4 was permanently disabled in
or1200_defines.v to give some better timings when or1200 is being
synthesized as a macro and part of bigger block. Unfortunately there is so
many combinations of defines that not all can always be tested (I'll
increase number of combinations in regression).

I have also updated that the second iteration in regression test 1:2 ratio.
Just update your local sources of orp_soc and run ../bin/run_rtl_regression
script in directory orp_soc/sim/run. Iteration 2 (pass 2) will test 1:2
ratio and it should pass successfully.

regards,
Damjan

----- Original Message -----
From: "Michael Scott" <mike.scott@jennic.com>
To: <openrisc@opencores.org>
Sent: Monday, April 07, 2003 5:50 AM
Subject: RE: [openrisc] Running slower wishone interfaces


> Hi Damjan,
>          Did you have any success running slower wishbone interfaces
> with modelsim 5.6 ?
>
> For the moment I'm up & running with a system with wishbone/RISC clock
ratio
> of 1:1
>
>
> Regards,
>
> Mike
>
>
>
> -----Original Message-----
> From: owner-openrisc@opencores.org
> [mailto:owner-openrisc@opencores.org]On Behalf Of Damjan Lampret
> Sent: 01 April 2003 23:08
> To: openrisc@opencores.org
> Subject: Re: [openrisc] Running slower wishone interfaces
>
>
> Mike,
>
> I'm going to have a closer look at this at the end of this week, I'm also
> going to try with Modelsim.
>
> regards,
> Damjan
>
> ----- Original Message -----
> From: "Michael Scott" <mike.scott@jennic.com>
> To: <openrisc@opencores.org>
> Sent: Monday, March 31, 2003 2:37 AM
> Subject: [openrisc] Running slower wishone interfaces
>
>
> > Hi All,
> >       I've just managed to get the OpenRISC core running under Modelsim
> 5.6.
> > However
> > It only seems to work with the Risc clock & Wishbone clock running at
1:1
> > I've tried changing the appropriate defines and the clmode input for 1:2
> and
> > 1:4 ratios
> > but the instruction address doesn't appear increment correctly. Instead
of
> > fetching
> > from 0x100, 0x104, 0x0108  it follows 0x100, 0x108, 0x110
> > This looks suspiciously like a clock domain issue and a missing
> synchroniser
> > somewhere but
> > I've checked the code & defines and it seems ok
> >
> > Has anybody successfully run the core under modelsim with slower
> > (half/quarter speed)
> > wishbone interfaces on instruction/data memories ?
> >
> >
> > Regards,
> >
> > Mike Scott
> >
> > ___________________________________________________
> > Jennic Ltd, Furnival Street, Sheffield, S1 4QT,  UK
> > www.jennic.com  Tel: +44 (0) 114 2812655   Confidential
> > ___________________________________________________
> >
> >
> >
> >
>
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